1. Field of the Invention
The present invention relates to a semiconductor device including test element group (TEG) elements and its manufacturing method.
2. Description of the Related Art
Generally, in a method for manufacturing a semiconductor device (wafer), TEG elements are formed in the semiconductor device, so that the electrical properties thereof can be evaluated by contacting probes to the TEG elements.
In a first prior art semiconductor device (wafer) (see: JP-2002-313864-A), a semiconductor wafer is divided into product chip areas. Also, TEG elements are formed beneath electrode pads in each of the product chip areas, while test electrode pads are formed in scribe line areas. The TEG elements are electrically connected to the test electrode pads. Therefore, the electrical properties of the semiconductor wafer can be evaluated by contacting probes to the test electrode pads.
In the above-described first prior art semiconductor device (wafer), since the TEG elements are covered by the electrode pads in the product chip areas, a third party including users cannot observe the TEG elements. In addition, after the semiconductor wafer is diced and assembled into chip packages, the test electrode pads in the scribe line areas are scrapped. Therefore, the electrical properties of the semiconductor wafer are never evaluated by a third party including users. Also, since the TEG elements and the test electrode pads do not require additional occupied areas, the integration of the product chips is not affected. Further, since the TEG elements and the test electrode pads are formed simultaneously by the manufacturing steps for the other portions of the product chip areas, the manufacturing cost hardly increases. Still further, since test chip areas for only TEG elements are not included in the semiconductor wafer, the manufacturing steps are not so complex, which also would not increase the manufacturing cost.
In the above-described first semiconductor wafer, however, after the semiconductor wafer is diced and assembled into chip packages, it is impossible for the manufacturer per se to evaluate the electrical properties of the semiconductor wafer. Note that, even after the semiconductor wafer is diced and assembled into the chip packages, the electrical properties of the chip packages are often required to be evaluated under various environments such as temperature environment and humidity environment.
In a second prior art semiconductor device (wafer) (see: JP-9-321104-A), a semiconductor wafer is also divided into product chip areas. Also, TEG elements are formed beneath main electrode pads in each of the product chip areas, and sub electrode pads (test electrode pads) are formed in each of the product chip areas. The TEG elements are electrically connected to the test electrode pads as well as the main electrode pads. Therefore, the electrical properties of the semiconductor wafer can be evaluated by contacting probes to the test electrode pads.
In the above-described second prior art semiconductor wafer, even after the semiconductor wafer is diced and assembled into chip packages, since the test electrode pads are not scrapped, the manufacturer per se can evaluate the electrical properties of the semiconductor wafer. Also, since the TEG elements and the test electrode pads are formed simultaneously by the manufacturing steps for the other portions of the product chips, the manufacturing cost hardly increases. Further, since test chip areas for only TEG elements are not provided in the semiconductor wafer, the manufacturing steps are not so complex, which also would not increase the manufacturing cost.
In the above-described second prior art semiconductor wafer, however, although the TEG elements are covered by the main electrode pads, even when the semiconductor wafer is diced and assembled into chip packages, the test electrode pads are not scrapped. Therefore, a third party including users can easily evaluate the electrical properties of the semiconductor wafer. Also, since the sub electrode pads (test electrode pads) are required in each of the product chip areas, the integration would be negatively affected. Further, bonding wire of the main electrode pads would be short-circuited to the sub electrode pads (test electrode pads).
In a third prior art semiconductor device (wafer), a semiconductor wafer is divided into product chip areas where TEG elements are not formed and test chip areas where various kinds of TEG elements and their test electrode pads are formed.
In the above-described third prior art semiconductor wafer, even after the semiconductor wafer is diced and assembled into chip packages, since test chip packages are obtained, the manufacturer per se can evaluate the electrical properties of the semiconductor wafer. Also, since the TEG elements are not included in the product chip areas, the electrical properties of the semiconductor wafer are never evaluated by a third party including users. Further, since the product chip areas do not require additional occupied areas, the integration of the product chips is not affected.
In the above-described third prior art semiconductor wafer, however, since the manufacturing steps for the product chip areas are different from those for the test chip areas, the manufacturing steps become complex, which would increase the manufacturing cost. Particularly, the result of the test chip areas by chemical mechanical polishing (CMP) steps and etching steps affects the product chip areas. As a result, the properties of the product chips would deteriorate.